1. Field of the Invention
Example embodiments of the present invention relate generally to a memory device and method thereof, and more particularly to a memory device and method of programming the memory device.
2. Description of the Related Art
A conventional multi-level cell (MLC) flash memory device may store a plurality of data in a single cell of NAND flash memory (e.g., based upon multiple threshold voltage level ranges, with each range associated with a different logic level or data state).
FIG. 1 is a table illustrating a relationship between memory cell data of a MLC flash memory and a threshold voltage of a memory cell. Referring to FIG. 1, data states “0”˜“3” of the memory cell may be configured such that lower-valued data states are associated with lower threshold voltages and higher-valued data states are associated with higher threshold voltages. The data of a memory cell may enter into a state “0” due to an erasing operation and may move to a higher-level state corresponding to a higher threshold voltage of the memory cell due to a programming operation. If a memory cell stores 2 bits of data, the 2 bits may be divided into most significant bit (MSB) data and least significant bit (LSB) data.
FIG. 2 illustrates a conventional process of programming the MLC flash memory of FIG. 1. Referring to FIG. 2, during memory cell programming, LSB data may be first programmed, followed by a programming of MSB data. If programming data of MSB data or LSB data is set to a first logic level (e.g., a higher logic level or logic “1”), the threshold voltage of a memory cell may not be changed during a programming operation and the data thereof may not be changed. Alternatively, if programming data of MSB data or LSB data is set to a second logic level (e.g., a lower logic level or logic “0”), the threshold voltage of a memory cell may be changed during a programming operation and accordingly the data thereof may be changed.
Referring to FIG. 2, the respective states “0” ˜“3” may be characterized by
State “0”: MSB=“1”, LSB=“1”
State “1”: MSB=“0”, LSB=“1”
State “2”: MSB=“1”, LSB=“0”
State “3”: MSB=“0”, LSB=“0”
Referring to FIG. 2, a transition between states will now be described. For example, if the memory cell is erased or at state “0”, the memory cell may transition to state “2” if LSB data transitions from the first logic level (e.g., a higher logic level or logic “1”) to the second logic level (e.g., a lower logic level or logic “0”) during a programming operation. In another example, if the memory cell is at state “1”, the memory cell may transition to state “3” if LSB data transitions from the first logic level to the second logic level during a programming operation.
Referring to FIG. 2, if the memory cell is at state “2”, the memory cell may transition to state “3” if MSB data transitions from the first logic level (e.g., a higher logic level or logic “1”) to the second logic level (e.g., a lower logic level or logic “0”) during a programming operation. Alternatively, if the memory cell is at state “0”, the memory cell may transition to state “1” if MSB data transitions from the first logic level to the second logic level during a programming operation.
Referring to FIG. 2, during a read operation, LSB data may be read out, following by reading out MSB data. If the LSB data is read out while the memory cell is at either of states “0” or “1”, the LSB data may be “1”. Alternatively, if the LSB data is read out while the memory cell is at either of states “2” or “3”, the LSB data may be “0”. Thus, a logic level of LSB data may be sufficient to determine whether the memory cell is at one of states “0” and “1” or at one of states “2” and “3”.
Referring to FIG. 2, during a read operation, if the MSB data is read out while the memory cell is at either of states “0” or “2”, the MSB data may be “1”. Alternatively, if the MSB data is read out while the memory cell is at either of states “1” or “3”, the MSB data may be “0”.
Accordingly, it will be appreciated that three (3) operations may be required, based upon the read MSB and LSB data, to determine state-specific information of the memory cell, such as whether the memory cell is at state “0” or a greater state, whether the memory cell is at a state less than or equal to state “1”, whether the memory cell is at a state less than or equal to state “2”, and/or whether the memory cell may have a state less than or equal to state “2” or a state “3”, etc.
Accordingly, in a conventional process of programming an MLC flash memory device, a higher number of operations may be performed to read out data from a memory cell, which may thereby increase a programming time.